Eye Diagram Explained: How to Read Eye Height, Width, and Jitter on High-Speed PCBs

By GW | Last updated: November 2026 (Updated November 2026)

In the world of electronics, an eye diagram examines serial communication channels rather than human anatomy, while its waveform shape resembles a part of the eye. According to Signal Integrity Journal’s PCIe 7.0 CEM channel validation study, PCI Express links have increased speed from 2.5 GT/s in earlier generations to 64 GT/s in PCIe 6.0 and 128 GT/s in PCIe 7.0. In the same regard, a symbol unit interval has decreased from 400 ps to 15.625 ps. With these increased speeds, skin effect and dielectric loss in the copper traces cause signal distortion and unwanted reflections that can close the unequalized eye before it reaches the receiver latch.

What Is an Eye Diagram in High-Speed Electronics?

On high-speed channels, an eye diagram is a statistical persistence image created on an oscilloscope that overlays consecutive unit-interval segments onto a composite window to reveal amplitude attenuation, inter-symbol interference, and timing jitter across millions of captured symbol periods during link verification.

Every serial link transmits a continuous stream of symbols across a PCB trace or cable. In Compliance Magazine’s technical guide to eye diagrams illustrates this folding process using all eight 3-bit sequences (000 through 111). Superimposing those eight bit patterns onto a single time window folds rising edges, falling edges, and steady rails into one composite graph. The vertical axis is signal amplitude in millivolts (mV). The horizontal axis represents time normalized to a unit interval.

The duration of one unit interval equals the reciprocal of the symbol rate. In binary Non-Return-to-Zero (NRZ) signaling, one symbol represents one bit period. A 10 Gbps NRZ stream has a 100 ps UI. A 25 Gbps Ethernet lane narrows that window to 40 ps. At 32 GT/s in PCIe 5.0, one UI lasts 31.25 ps. Signal Integrity Journal’s PCIe 7.0 CEM channel validation study tracks this progression across generations. PCI Express bandwidth scaled from 2.5 GT/s in the early 2000s to 64 GT/s in PCIe 6.0 and 128 GT/s (64 GBaud PAM4, 15.625 ps UI) in PCIe 7.0.

A single-shot waveform capture shows a short duration of time and only captures a few dozen bits. Rare transition errors are hidden in these waveform captures. Color-graded persistence, a diagnostic tool, can display millions of transitions and generates a two-dimensional density histogram. Rare signal trajectories across transitions are shown in cold blue and green pixels. Warm red and yellow pixels indicate where the data signal spends most of its time in this illustration. Engineers use this display to verify digital audio, uncompressed video links, and multi-gigabit server backplanes. An open central region of a display indicates margin in timing and voltage for samples displayed, and rare jitter and noise may require a statistical tail analysis.

How to Read Eye Height, Eye Width, and Crossing Percentage

You read an eye diagram by measuring six core geometry metrics on the display. These metrics are, logic 1 and logic 0 voltage rails, eye amplitude, vertical eye height, horizontal eye width, crossing percentage, and edge rise and fall times. All six of these readouts define the opening and quantify link performance under load.

Engineers often confuse eye amplitude with eye height. Eye amplitude is the difference between the mean logic 1 voltage (V_1,mean) and the mean logic 0 voltage (V_0,mean). Per Sierra Circuits’ high-speed PCB eye diagram guide, oscilloscopes sample both rail means across the central 40% to 60% of the horizontal time axis. Eye height is the vertical distance between inner rail boundaries. A 3-sigma histogram readout uses fixed statistical bounds, while BER-based eye height uses inner contours calculated for the specified error probability. In Compliance Magazine’s waveform measurement breakdown illustrates how vertical histograms define these rail boundaries.

Using 3-sigma oscilloscope vertical histogram bounds, the instrument calculates:

Eye Amplitude = V1_mean – V0_mean;
Eye Height (3-sigma) = (V1_mean – 3 × sigma_1) – (V0_mean + 3 × sigma_0);
Crossing Percentage = 100 × (V_cross – V0_mean) / (V1_mean – V0_mean).

Horizontal eye width measures the clear time window between the rising and falling crossing histograms at the slicing level. Crossing percentage locates where the rising and falling edges intersect relative to the logic rails. A crossing point away from the mid-rail level indicates vertical crossing asymmetry. That shift can arise from unequal rise and fall slew rates or duty-cycle distortion (DCD), where high and low pulse widths are unequal. Sierra Circuits’ signal transition analysis notes that rise and fall times are measured between the 10% and 90% thresholds. Engineers also use 20% and 80% or 30% and 70% thresholds to avoid pre-shoot artifacts. Maintaining clean edge symmetry on dense multilayer boards requires balanced stackups, as detailed in our 8-12 layer PCB stackup and impedance control guide.

How Jitter Narrows Eye Width: TJ, RJ, DJ, and DCD Explained

Jitter narrows the horizontal eye width by shifting signal zero-crossings earlier or later than the ideal recovered clock instant. Unbounded Gaussian Random Jitter (RJ) increases with observation depth, whereas Deterministic Jitter (DJ) is bounded. In order to calculate Total Jitter (TJ) at the target bit error rate, engineers have to separate RJ from DJ.

As stated in Sierra Circuits’ timing margin evaluation, timing margin rapidly diminishes as total jitter approaches 0.5 UI. In the Dual-Dirac jitter model, total jitter of 0.5 UI results in a horizontal eye width of 0.5 UI at the target BER before accounting for receiver sampling window requirements. Total jitter is made up of two components:

• Random Jitter (RJ) is modeled by a zero-mean, unbounded, Gaussian timing noise, and is caused by thermal noise, shot noise and flicker noise in the oscillators and reference clocks. Gaussian tails extend to positive and negative infinity and therefore peak-to-peak RJ scales with the target BER.
• Deterministic Jitter (DJ) consists of bounded timing deviations with a physical cause. DJ is made up of Data-dependent Jitter (DDJ, caused by inter-symbol interference across varying bit pattern runs), Duty-cycle distortion (DCD), and other types of jitter.

The tail multipliers used by the Dual-Dirac model are derived from NIST Gaussian normal probability tail functions. Using the above, Total Jitter at a given BER is:

TJ(BER) = DJ_delta_delta + 2 × Q(BER) × sigma_RJ; Eye Width(BER) = 1 UI – TJ(BER)

For a binary NRZ link requiring 10 -12 BER, the Gaussian tail factor is Q = 7.0345, so 2 × Q = 14.069. Therefore, 2 × Q = 14.069. Let’s look at a sample problem for a 25 Gbps NRZ link (1 UI = 40 ps). Assumed inputs: We’ll assume DJ dd = 8.0 ps and sigma RJ = 1.5 ps. We multiply 14.069 by 1.5 ps to get 21.1 ps random jitter. We add 8.0 ps of DJ to get total jitter (TJ) for 10-12 BER = 29.1 ps. This leaves an open horizontal eye width = 40 ps – 29.1 ps = 10.9 ps (0.27 UI). A short 1,000-bit oscilloscope capture may miss Gaussian tail excursions and overestimate horizontal eye margin. Vertical eye height may provide cleaner voltage margin. Measured p-p jitter of an eye only describes captured samples and doesn’t describe total jitter at the target BER.

In PAM4 links, jitter analysis is even more strict. Signal Integrity Journal’s PAM4 validation analysis notes that in PAM4 links, jitter evaluation can’t depend on just 2 NRZ transition edges with respect to the recovered clock, as is the case in binary NRZ links. Instead, it must analyze 12 directed transitions across all four symbol states. That 12-edge analysis captures level-dependent skew and voltage non-linearity.

Why does an eye diagram with a thin single rail perform better than one with a thick fuzzy rail?

A thin single rail on an oscilloscope eye diagram visual representation (or eye pattern) indicates tightly repeatable logic voltage levels across all high-speed digital signal bit transitions. That repeatability maximizes vertical noise margin. A thick fuzzy single rail indicates amplitude dispersion, probably from thermal noise, uncompensated ISI, and/or crosstalk.

From Oscilloscope Eye Opening to 10^-12 BER Contours and Bathtub Curves

Contouring BER curves helps translate finite eye captures into statistical bit error rate (BER) predictions down to 10^-12 or 10^-15. These contours connect points of equal error probability across voltage and time. The bathtub curve is a horizontal slice through the center of the ber contours.

Real-time oscilloscope persistence overlays thousands to millions of unit intervals and directly observes only the 10^-3 to 10^-6 probability region. Proving 10^-12 BER margin therefore requires Gaussian random-jitter tail extrapolation or statistical eye convolution. By binomial confidence math (1 – 0.05^1/N ≈ 3/N), observing zero errors in 10⁶ captured bits bounds the error probability to roughly 3 × 10^-6. MDPI Electronics’ statistical eye diagram research shows why brute-force transient simulation can’t bridge that gap. Time-domain transient simulation must sample 50, 64, or 100 points per unit interval. Running 10¹² bits in transient mode would exhaust workstation memory. Statistical eye simulators solve this by convolving the channel single-bit pulse response with transition probabilities. They also account for line encodings like 8B/10B or TMDS where transition probability shifts above or below 0.5.

In PCIe 6.0 and PCIe 7.0 PAM4 links, raw physical channels don’t hit 10^-12 BER directly at the slicer. PCI-SIG’s PCIe 6.0 FEC and FLIT error-correction specification overview explains this multi-layer architecture. The equalized receiver targets a pre-FEC First Bit Error Rate (FBER) strictly below 10^-6. Lightweight 3-way interleaved Forward Error Correction (FEC) across fixed 256-byte FLITs then works with CRC detection and link-level FLIT retry to reach 10^-12 link reliability.

How does eye diagram mask testing verify protocol compliance?

Eye-mask testing examines sampled data to see if any waveform enters a predefined keep-out region. (Sierra Circuits) Six points along an inner limit combine with outer limit voltage levels to define the keep out region. Full protocol compliance mandates that mask testing be performed along with jitter, return loss, and an equalized receiver BER test.

6 Eye Diagram Distortion Patterns and What Causes Them

Eye-diagram distortion shapes identify possible physical layer issues on the board. Vertical compression points to channel loss, double rails point to ISI, reflections, or over-equalization, fuzzy rails indicate crosstalk, and a tilted crossing indicates differential skew.

Increasing voltage swing when an eye closes in the channel worsens near-end crosstalk and wastes power. In channels from PCIe 3.0 onward, each end of the channel (transmitter and receiver) is equalized to help recover an eye closed by channel ISI. A closed, unequalized passive eye, therefore, doesn’t necessarily indicate channel failure. For PCIe 6.0 and 7.0 PAM4 channels, Signal Integrity Journal’s CEM channel compliance study states that a clear pass/fail benchmark is provided. The reference receiver must be equalized in such a way that it hits a pre-FEC FBER target of 10^-6 in order to meet the 10^-12 BER target.

One of the most harmful board defects is an unused through-hole via barrel acting as an open-ended quarter-wave stub. Its first insertion-loss resonance occurs at:

f_res = c / (4 × L_stub × sqrt(Dk_eff)).

Assumed inputs: effective dielectric constant Dk_eff = 4.0 and speed of light c = 11.8 in/ns. On a thick backplane, a 120 mil (0.120 in) via stub resonates at 12.3 GHz. That places a deep attenuation notch at 25-28 Gbps NRZ signals. On a standard multilayer board, a 60 to 80 mil stub resonates between 18.4 GHz and 24.6 GHz. That notch distorts 32 GT/s PCIe 5.0 and 64 GT/s PCIe 6.0 channels, as studied in via-stub resonance studies in IEEE Xplore. To verify channel loss on production panels, IPC-TM-650 Method 2.5.5.12A defines five insertion-loss test methods, including Single-Ended TDR to Differential Insertion Loss (SET2DIL, Method D) and frequency-domain VNA S-parameters (Method E). SET2DIL captures total coupon insertion loss including via transitions. The total loss combines electrical conductor and dielectric loss mechanisms.

6-Signature Eye Closure Diagnostic Map

This diagnostic matrix links six oscilloscope eye distortions (with sub-cases for ISI vs. Over-Equalization and NEXT vs. FEXT) to their electronic mechanisms and root causes on PCBs and lab tests that confirm them.

NRZ vs. PAM4 Eye Diagrams Across PCIe, Ethernet, USB, and DDR

An NRZ eye diagram uses two voltage levels to transmit 1 bit per unit interval with a single eye opening. A PAM4 eye diagram uses four voltage levels to transmit 2 bits per unit interval. At equal total voltage swing and equally spaced levels, PAM4 stacks three vertical eyes and incurs a 9.54 dB vertical SNR penalty.

Packing two bits into each symbol cuts the Nyquist fundamental frequency in half compared to NRZ. PCIe 6.0 transmits at 64 GT/s using 32 GBaud PAM4 with a 16 GHz Nyquist frequency. PCIe 7.0 doubles the throughput to 128 GT/s using 64 GBaud PAM4 and a 32 GHz Nyquist frequency. However, dividing the same total transmitter voltage swing across three vertical eye openings reduces adjacent-level spacing to one-third (20 × log₁₀(3) ≈ 9.54 dB SNR penalty). In PAM4 channels, ISI and unequal transition timing across the 12 directed transitions also affect the three horizontal eye openings. Signal Integrity Journal’s 128 GT/s PAM4 CEM channel tests found a roughly 33% loss in available horizontal eye size compared to NRZ, under similar conditions.

To account for uneven compression of PAM4 eyes, strict requirements on Level Separation Mismatch Ratio (R_LM) are defined in standards. Signal Integrity Journal’s PCIe 7.0 transmitter requirements specify a minimum SNDR of 34 dB, and uncorrelated total jitter of 2.0 ps peak-to-peak. The requirement also defines R_LM to be 0.95, and filtered reference-clock phase jitter to be less than 67 femtoseconds RMS. In multi-gigabit links from PCIe 3.0 to PCIe 7.0, an unequalized physical eye at the receiver pin is permitted to look completely closed under the specification. Compliance is judged by the virtual eye after Reference Receiver Equalization (CTLE, FFE and DFE). In the higher frequencies of 16-32 GHz, high-frequency substrate loss becomes the primary constraint. We discuss high frequency physics in our high-frequency RF and microwave PCB design guide.

When a Closed Eye Is Still Compliant: Pre-Emphasis, CTLE, and DFE

A high-speed signal eye often looks completely closed when probed directly at the receiver package pin (TP4). Passive PCB copper and dielectric losses cause severe inter-symbol interference (ISI) across the channel. The link still passes compliance because the transmitter FFE and on-die receiver CTLE and DFE filters refine the frequency response and cancel post-cursor ISI at the decision point.

Probing a multi-gigabit BGA ball with an oscilloscope without a reference receiver filter causes false failure readings. Most recent SerDes channel architectures partition equalization across three stages, as illustrated in IEEE 802.3ck 100G electrical channel reference receiver evaluations:

1. The transmitter Feed-Forward Equalization (Tx FFE) stage uses a finite impulse response (FIR) filter at the transmitter to apply pre-shoot (pre-cursor tap) and de-emphasis (post-cursor tap) equalization. This pre-shoot attenuates low-frequency run amplitude, and allows high-frequency edges to arrive with equal amplitude after PCB loss.
2. The receiver uses continuous time linear equalization (Rx CTLE) to boost high-frequency signal content and flatten the channel frequency response. Since CTLE is a linear process that reduces ISI, excessive peaking also amplifies high-frequency crosstalk.
3. Decision Feedback Equalization (Rx DFE) uses a non-linear feedback loop based on previously sliced symbols to subtract post-cursor inter-symbol interference at the decision point without amplifying incoming noise. However, a large noise spike can cause a single symbol error that DFE tap feedback propagates into a burst error. That burst mechanism is why PCIe 6.0 and 7.0 specify First Bit Error Rate (FBER) and pair DFE with 3-way interleaved FEC, CRC detection, and link-level FLIT retry (PCI-SIG).

The core of any high-speed SerDes receiver is an equalizer. Physical probes can’t reach inside the silicon die after the Decision Feedback Equalizer (DFE) summer. Instead, tests performed in the lab use IBIS-AMI simulations or query on-die Eye Monitors. An example is the USPTO Patent US10845402B2, in which an on-die equalizer tap adjustment solution reconstructs the eye. Physical PCB stack-up structure reduces raw channel loss before the signal enters the receiver equalizer.

PCB Layout, Stackup, and Laminate Choices That Keep the Eye Open

To keep a high-speed PCB eye open, one needs to consider the laminate dissipation factor (Df), copper foil roughness, glass-fabric weave style, and via-stub length, among other factors, in relation to the expected Nyquist frequency. Use of low-loss laminates and high-volume low-pressure (HVLP) copper reduces attenuation. Additionally, spread glass reduces weave-induced skew and back-drilling or HDI microvias reduce via-stub reflections.

Equalization can account for smooth frequency dependent dielectric loss. Deep quarter-wave via-stubs limit the recovery, and glass-weave skew introduces unequal propagation delays that shrink the differential eye opening. For 128 GT/s PAM4 links, Signal Integrity Journal’s PCIe 7.0 routing constraints cap total pad-to-pad channel loss at 32 GHz at approximately -36 dB. That budget sets a baseline where PCB traces must exhibit less than 1.0 dB of insertion loss per inch (2.5 cm) at Nyquist. For other serial standards, dividing the trace-loss allocation in dB by the routed trace length gives the allowable average trace loss per unit length. Simultaneously, IEEE Xplore research on high-speed via-stub resonance confirms that trimming unused through-hole barrels via controlled-depth backdrilling pushes resonant notches above the signaling band.

Laminate dielectric constant, dissipation factor, and copper-foil roughness all vary with glass-weave, pressed resin content, and test frequency. Final stackup release must use the pressed prepreg impedance and loss calculation of the fabricator. Engineers scaling up from complex 16-24 layer PCB lamination and blind/buried vias to 32-42 layer PCB stackups and signal integrity must finalize their material selection early. Rogers and low-loss high-speed PCB manufacturing integrate well with HDI microvia PCB fabrication, thus eliminating resonant through-hole stubs on dense SERDES breakouts.

High-Speed PCB Laminate and Via-Stub Budget Matrix

This nine-row synthesis matrix relates data-rate tiers, serial protocols, laminate Df tiers, roughness profiles of copper, weave styles of fiberglass, and architectures of via-stub control.

How to Set Up an Oscilloscope and Clock Recovery for Eye Diagram Analysis

Analyzing an eye diagram across serial protocols requires an understanding of the harmonic structure of your signal and an oscilloscope and probe bandwidth matched to that structure, as well as a Golden PLL clock recovery filter matched to the bandwidth of the protocol loop, and de-embedded S-parameters for all test fixtures and cables.

A misconfigured lab equipment setup can make a compliant PCB appear to have defects or hide real jitter. Before condemning your board, verify the following five steps:

1. Select proper instrument bandwidth based on your modulation format. A sampling oscilloscope, as described in the Sierra Circuits oscilloscope setup guide, requires a bandwidth of 1.5 to 2 times the signal frequency. For PAM4 links, Signal Integrity Journal’s PCIe 7.0 measurement guidelines mention that for PCIe 6.0, a 50 GHz minimum real-time oscilloscope bandwidth is required. PCIe 7.0 (128 GT/s) increases the minimum real-time scope bandwidth to 65 GHz to capture second-harmonic energy at 64 GHz.
2. Account for oscilloscope timebase distortion and intrinsic noise floor. NIST research on oscilloscope timebase distortion and measurement uncertainty shows that the eye jitter displayed on an oscilloscope is the RSS of channel impairments and noise intrinsic to the measurement instrumentation. Always calibrate and correct the horizontal timebase distortion. The vertical signal can be scaled to fill the ADC dynamic range.
3. Configure the Golden PLL Clock Data Recovery (CDR) to the exact protocol specification (for example f_baud/1667 or PCIe’s specified phase-locked loop order). A CDR loop bandwidth set too wide will track low-frequency periodic jitter and artificially increase eye width.
4. Choose a PRBS length that’s representative of the type of jitter that you would like to stress. Short patterns like PRBS7 (2 7 – 1 = 127 bits) stress rapid edge transitions. Long patterns like PRBS31 (2 31 – 1 bits) expose long-run baseline wander and deep inter-symbol interference.
5. Use the on-die Lane Margining Receiver (LMR) for field-deployed systems. The Signal Integrity Journal notes that PCIe links running at 16 GT/s and above in the L0 state can support built-in LMR. Software can sweep timing and voltage margins (if supported) on deployed systems.

What to Specify to Your PCB Manufacturer to Lock In Eye Diagram Margin

To manage process variations versus what is simulated in an eye diagram, authorize the pressed stackup table prior to layout release. Define exact laminate slash sheets, controlled-impedance tolerances, backdrilled via-stub limits, IPC-TM-650 2.5.5.7A TDR coupons, HVLP copper roughness limits, and IPC-TM-650 2.5.5.12A insertion loss.

Writing “FR-4 or equivalent, 100 ohm differential” on a fabrication drawing invites unannounced material substitutions that erode eye height in production. IPC-6012 Class 2 or Class 3 defines board acceptance criteria. Advanced fabrication lines also support fine trace/space down to 2 mil (0.002 in), ±5% controlled-impedance tolerances, and 24-hour prototype turnaround (Sierra Circuits). Fabricators verify trace impedance on dedicated panel TDR coupons per IPC-TM-650 Method 2.5.5.7A before shipping boards. Panel-edge controlled-impedance and insertion-loss coupons (TDR and SET2DIL coupons) verify batch trace geometry and dielectric consistency. System-level eye margin still depends on connector transitions, package parasitics, and transceiver equalizer tap weights.

Every production panel we fabricate undergoes cross-section validation, AOI and TDR controlled-impedance testing and PCB inspection.

Frequently Asked Questions