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Controlled-Impedance HDI · High-Speed Digital
Controlled-Impedance HDI PCBs for High-Speed Digital — DDR5, PCIe 5.0, USB4 & 100GbE
At DDR5 and PCIe 5.0 edge rates, the board ceases to be just a link and becomes a transmission line. PCBark engineers high-speed HDI PCBs with controlled impedance, low-loss laminates, and signal-integrity verification—so the channel that passes in the simulation is the one that ships to you.
Specifications
Controlled Impedance
±10% / ±5%
Controlled impedance, standard / on request with TDR coupon
Low-Loss Laminates
Low-loss
Megtron-class & ultra-low-loss laminates stocked
Copper-Filled Microvia
~100 µm
Copper-filled microvia, 0.75:1 aspect ratio
PCIe 5.0 Lane Rate
32 GT/s
PCIe 5.0 lane rate; DDR5, USB4 40 Gbps, 100GbE
IPC-6012 Class 3
Class 3
Built & inspected to IPC-6012 Class 3
EMS Experience
16+ yrs
EMS experience, 500,000 m²/yr capacity
01 / Bring-Up
When Standard PCBs Can’t Keep Up With High-Speed Signals
It only shows up during bring-up, not during layout on the schematic. A link trains down a grade, DDR5 write margin disappears or a PCIe 5.0 lane shows correctable errors that never should have been there, and everything in the layout just looked… clean. Exactly what gets you to the surprise. Above a few Gb/s, copper between two pins looks and behaves just like a transmission line, and the board itself starts attenuating, reflecting and skewing the signal long before the silicon even sees it. This is where an ordinary printed circuit board becomes a high speed pcb — an engineered board rather than a routed one.
02 / Structural Fix
The Structural Fix
A high-speed HDI PCB is structural fix: The top two failure mechanisms, loss and reflection, are handled.
Loss
loss means “Loss,” caused by a dielectric with a dissipation factor (Df) that slowly bleeds energy out of the signal in the form of heat. The higher your data rate, the more hungry that loss gets.
Reflection
reflection means “Loss and Echo.” Echo means reflection by any “impedance” discontinuity, such as trace whose impedance wanders off target or a via stub that resonates. controlled impedance manufacturing construction ties trace geometry down such that its impedance stays on-target along the full channel, and it swaps through-holes for short copper-filled microvias with minimal stubs to eliminate this loss mechanism.
Result
What remains is a board which reliably presents your edge rate at the signal and which preserves signal integrity to that rate.
03 / Budget & DFM
A Loss & Reflection Budget
Honestly speaking, what this capability page describes is not a material brochure, it’s a loss and reflection budget. While a DDR5 link over a short channel may be made to close with a mid-loss laminate and up to 10% impedance at the signal interface, a PCIe 5.0 or 100GbE interface over longer reaches must use a low-loss laminate, lower impedance, and backdrilling/microvias. On this page — and again in our DFM review — we simply figure out what the cheapest option is that will still make your link pass. There is no sense in designing you into an expensive board you don’t need.
01 / Capabilities
PCBark High-Speed HDI Capabilities — Impedance, Microvia Structures & Layer Count
What matters to a hardware engineer, for a capability page, are numbers. These numbers describe what that line is actually going to hold, and what we are going to check for at DFM. Below, is our actual working-envelope for our high-speed PCB manufacturing line on controlled-impedance builds; what can be achieved on your board will vary, of course with such parameters as copper weight, dielectric thickness, stackup, and the layer count. We lock these values in our design not in a flashy claim here. Be sure to compare against the right hand column below as this represents the baseline against which comparison quotations should be made, not some “maximum possible” value.
| Parameter | Capability | Reference |
|---|---|---|
| Controlled impedance tolerance | ±10% standard; ±7% / ±5% on request | IPC-2141 / verified by TDR coupon |
| Impedance targets | 50 Ω single-ended, 90 / 100 Ω differential, custom | Confirmed at DFM |
| Microvia | Copper-filled stacked & staggered, ~100 µm, aspect ratio 0.75:1 | IPC-2226 / IPC-6012 |
| Line / space | Down to ~75 µm on advanced builds | Confirmed at DFM |
| Via stub control | Backdrilling on through-hole transitions; microvia in HDI region | PCBark process |
| Laminates | High-Tg FR-4, mid-loss, low-loss (Megtron-class), ultra-low-loss | Manufacturer datasheets |
| Reliability class | Built & inspected to IPC-6012 Class 3 | IPC-6012 |
| Verification | TDR impedance coupon, SI review at DFM | PCBark in-house |
02 / Engineering Note
Why Microvias Matter at Speed
What quietly kills a high-speed channel is the via stub. A signal that drops from an outer layer to an inner layer in a long plated through-hole leaves the unused segment of the hole hanging as a stub, and that stub resonates at a frequency defined by its length – right in the band a PCIe 5.0 or 100GbE channel occupies. We kill it in two ways. In the HDI region, we use copper-filled microvias, which are inherently short and carry virtually no stub, making the vertical transition a no-reflection site. Where we still need through-holes – say, on a thick backplane – we backdrill the unused barrel after plating so that the stub length becomes insufficient to resonate at any relevant frequency. Both approaches target the same physics: in high-speed, the signal sees every impedance discontinuity as a partial mirror; the uncontrolled via is the biggest mirror in the entire board. Our stacked microvias have the additional advantage of reducing interconnect length, and this decreases the insertion loss, as a benefit of increased density. We absorb the added processing cost — both stacked filled vias and backdrilling add steps — and pay that premium only when a channel needs it, not as part of a blanket “high-speed premium.” When the driver is maximum interconnect density rather than channel loss — a fine-pitch BGA that simply will not fan out — that is an any-layer HDI build, which we cover on its own page.
03 / Purchaser Profile
Purchaser Profile — Engineering & Procurement
Every structure noted above maps directly onto a single line item in the quotation. So, it makes sense we list the standard tolerance as 10% and don’t lead with a 5%, since most of the DDR5 and any short PCIe routing will work adequately at the former, and most buyers end up paying for 5% they don’t need to use, which is often the primary over-cost in the high-speed board segment. Send us your RFQ: the impedance value needed, data rate, and max channel length will allow us to determine which laminate and which via strategy is truly required.
01 / Material Selection
Low-Loss Laminate Selection — FR-4 vs Megtron vs Rogers for DDR5, PCIe 5.0 & USB4
For a high-speed board, material selection is simply a matter of a loss budget expressed as a currency. We determine this based on the dielectric constant (Dk) and the dissipation factor (Df) for the selected laminate – the measures of signal attenuation over channel length – climbing the scale in cost and value as Df goes down. For guidance, this decision matrix links laminate classes to typically suited interface types; the numbers quoted in parentheses represent published ranges from vendor data sheets, and the optimal grade is always relative to the channel length just as much as to the data rate. Short links tolerate a more loss-priced material, long reaches cannot.
| Laminate class | Typical Dk / Df (at GHz) | Fits | When to step up |
|---|---|---|---|
| High-Tg FR-4 | Dk ~4.2–4.5 / Df ~0.02 | Lower-speed digital, short DDR4-class links | Loss eats the eye at DDR5 / PCIe rates |
| Mid-loss | Dk ~3.7–3.9 / Df ~0.008–0.012 | DDR5 over short–moderate channels | Channel length or rate pushes loss over budget |
| Low-loss (Megtron-class) | Dk ~3.4–3.7 / Df ~0.002–0.004 | PCIe 5.0 (32 GT/s), USB4 (40 Gbps), 100GbE shorter reach | Very long, high-rate channels |
| Ultra-low-loss | Dk ~3.0–3.4 / Df ~0.001–0.002 | Long 100GbE / 112G-class channels, low-jitter backplanes | This is the low-loss ceiling for digital |
02 / Engineering Reality
Df Over Dk, and Copper Roughness
Firstly, on a digital channel Df is far more important than Dk; Dk only really defines the impedance for your target DDR5 design whereas Df defines how much energy you lose per inch, and so when someone asks for a “Rogers board” on a DDR5 design the question is only really do you want it to be to a specific loss number or did you only just hear the name. Rogers laminatebs are definitely needed for RF and microwave in terms of stability of Dk across frequency, however for a high-speed digital channel, the cheapest path to the loss number is likely to be on a thermoset like a Panasonic Megtron 6 or equivalent megtron-class material, which also gives superior processability.
Secondly, the copper roughness silently adds loss at high frequency; because the signal runs over the surface of the conductor so a low loss build is a pairing of the laminate with a low-copper foil – that pairing comes as part of the specification of the board, not an afterthought. In the area where it folds, a rigid-flex high-speed circuit board does carry the dynamic element on a layer, but the rigid HDI carries the controlled-impedance routing – the junction between the two regions with a prepreg will be a controlled routing connection formed part of the planned DFM stackup.
03 / Buyer Advisory
Buyer Advisory — Specifying Material Without Overspending
You should never specify a laminate first; always specify the channel; tell us the data rate, the maximum electrical length and the desired impedance along with the desired layer. The loss model can then tell us the cheapest laminate type that actually works. I have seen DDR5 designs spec’d on an ultra low-loss material that could have actually been built on a medium-loss grade, and PCIe 5.0 backplanes spec’d on FR-4 which never stood a chance. The material specification of a board should be the subject of a DFM study before stack-up is ever defined.
01 / The Data
Controlled-Impedance HDI vs Standard Multilayer PCB — The Data
Brochures distinguish high, medium and low; this board requires a controlled-impedance; there is no distinction between high, medium and low on this page – only whether your board will close the channel or not. Below is the same DDR5 design built two ways — a standard multilayer PCB with conventionally drilled through-holes, and a controlled-impedance HDI build — across the parameters that truly determine channel closure.
| Parameter | Standard multilayer PCB | Controlled-impedance HDI PCB |
|---|---|---|
| Impedance tolerance held | Often uncontrolled or ±15–20% | ±10% standard, ±5% on request |
| Vertical transition | Plated through-hole + stub | Copper-filled microvia / backdrilled PTH |
| Via stub resonance | In-band on high-speed channels | Removed (microvia) or pushed out of band (backdrill) |
| Insertion loss at GHz | Higher (FR-4 + stub) | Lower (low-loss laminate + short via) |
| Min BGA pitch routable | ~0.8 mm | ≤0.4 mm |
| Layers for same fan-out | Higher | Lower (microvia density) |
| SI verification | Rarely provided | TDR coupon + DFM SI review |
| Relative fab cost | Lowest | Higher, offset by yield & fewer respins |
02 / Honest Costs
Honest Costs
Honest costs: a controlled-impedance board is more expensive to produce due to the cost of low-loss laminatebs, copper-filled microvias and impedance measurement. The unit cost does not account for the total cost of failure. The re-spin cost for a high speed product, not just the board but a schedule slippage and the need for an entire re-build and re-assembly of PCBs, could exceed the initial board cost by an order of magnitude.
Framing based on typical high-speed development cost structure (engineering schedule + re-fab + re-assembly). Your figures depend on volume and program timeline; we do not claim a fixed percentage.
Not sure whether your channel needs HDI or just backdrilling?
Get a build-strategy comparison for your stack-up →01 / Signal Integrity
Signal-Integrity Engineering — Simulation, Impedance Coupons & First-Pass Sign-Off
Many of the board manufacturers will claim that they can produce you a board according to the specification; the area that programs pay money is not having verified routing ( impedance) integrity. We remove that risk by verify, not guarantee, with signal-integrity in DFM. When there is a failure, instead of at bring up; the fixes are simple, cost-effective and occur early in the process, rather than later.
Impedance & Loss Review
Pre-tooling, we review your impedance targets and loss budget on the interface, ensuring that an trace which cannot hold the required 100-ohm differential in its assigned layer is flagged while it’s still inexpensive to fix.
Model, Compare & Reference Planes
We model and compare controlled-impedance traces to your target and highlight the insertion-loss and crosstalk risks on high speed pairs, and confirm the reference-plane scheme that places a solid ground plane adjacent to each signal layer.
Channel Sanity-Check vs Spec
For high-rate channels we do sanity-check the expected return loss and eye margin against the applicable interface specification-DDR5 timing, PCIe 5.0 channel loss, USB4 or 100GbE budgets-so that the board is shipped with a channel that’s guaranteed to carry the load.
02 / Engineering Note
The Impedance Coupon Is the Proof
An impedance coupon-a small test structure that mimics the trace geometry and layer assignment of your boards, placed on the same build panel-is measured post-fabrication with a TDR. That test method sends an edge signal down the trace and reads back the resulting impedance (measured as a series of values along the trace length) from the reflected signal, with point-by-point detail determined by the reflection profile of your channel. That number is evidence of build validity, and accompanies the finished job lot. Why should you care about coupons? Because impedance is set by the trace width, dielectric thickness, and copper thickness-all three of which will vary to some degree from target during fabrication due to the limitations of your tolerances. What the stack is claimed to build is one thing; what it actually did is entirely another. For a high-speed project, the latter claim is what prevents a lengthy and unpleasant debug cycle where the board, connector and silicon all become suspects at the same time.
01 / Application Results
Application Results — DDR5, PCIe 5.0, USB4 and 100GbE Build Outcomes
Interfaces that command high-speed HDI build require one attribute above all others: the channel budget is so restricted that the board can no longer be considered merely a static intermediary; rather, it is a part of the signal path. The matrix at left relates each interface requirement to its characteristic build; below, we have captured the results achieved by these builds as generic ranges instead of single advertised values.
| Interface | Approx. rate | Typical laminate class | Build characteristics |
|---|---|---|---|
| DDR5 | up to 6400+ MT/s | Mid-loss to low-loss | Tight length matching, ±10% impedance, controlled crosstalk |
| PCIe 5.0 | 32 GT/s per lane | Low-loss | Backdrill / microvia, tight differential 85–100 Ω, low insertion loss |
| USB4 | 40 Gbps | Low-loss | Differential pairs, short low-stub transitions |
| 100GbE | 25G/lane NRZ · 50G/lane PAM4 | Low- to ultra-low-loss | Ultra-low-loss laminate, backdrilling, smooth copper |
02 / Build Outcomes
Outcomes by Interface
Server / Memory — DDR5 Margin
Recovering DDR5 write margin on a dense memory board
A server-grade design lost its write margin on the longest byte lanes due to a combination of in-band stubs on data lanes and a too-tight impedance target that original stack-up couldn’t hold on its required layer set. Converting this to a controlled-impedance HDI board shifted the critical transitions to microvias, enabling capture of the single-ended and differential targets within 10%-confirmed via coupon measurements.
±10%Impedance held, TDR-verified
MicroviaStub removed on data lanes
6400+DDR5 MT/s target rate
Networking — PCIe 5.0 / Backplane
Closing a PCIe 5.0 channel over a long backplane reach
A networking platform called for PCIe 5.0 operation at 32 GT/s, across a distance where FR-4 insertion loss alone would have extinguished the eye. A build of laminate with low loss and through-hole transitions backdrilled to prevent the in-band stub resonance, and close impedance tolerances on the high-speed lanes, delivered the required channel performance. This work was validated against the relevant interface loss budget at DFM- not only at bring-up.
32 GT/sPCIe 5.0 lane rate
BackdrillStub resonance removed
Low-lossLaminate to hold loss budget
High-Speed I/O — USB4 / 100GbE
Holding the eye on a 40 Gbps USB4 and 100GbE I/O board
The 40 Gbps USB4-carrying high-speed board, which also included 100 Gbbe lanes, required that the differential-pair stay intact and the loss remain low for its long Ethernet channels. A low-to-ultra-low-loss laminate, which has smoother repaso to lower conductor-roughness loss, combined with short, low-stub USB4 transitions, helped minimize issues along with an SI review on high-rate lanes before production tooling.
40 GbpsUSB4 differential pairs
Smooth CuConductor-roughness loss cut
SI reviewBefore tooling
01 / Quality Compliance
Certifications & Quality Compliance
Most failures of high-speed boards escape the naked eye and require measurement and controls, not a visual check. To those ends, PCBark adheres to, inspects and certifies to the following references. Please inquire about the certificate number and dates for your specific project before proceeding.
02 / Standards
Standards & References
IPC-6012 Class 3
Performance & qualification, high-reliability rigid boards
IPC-2226
HDI design standard — microvia structures
IPC-2141
Controlled-impedance design reference
ISO 9001
Quality management system
TDR coupon
Impedance verified per lot
High-speed buyers concern themselves with Class 3 because it’s the highest grade of acceptance, which requires the tightest tolerances on hole- and plating defects which commonly evolve into intermittent high-speed failures. Used along with an impedance coupon and an HDI build to IPC-2226 standards, the process used for certification actually proves-rather than just document-that the channel designed has been produced.
01 / Procurement Guide
Procurement Guide — Cost Drivers, Lead Time & DFM Support
By the time an HDI board designed for high speed reaches a purchasing agent, the case for it’s design has generally been made: the questions remaining, now focused on value, lead time, and identifying design risk in the process, weigh cost, timeline, and the design changes that improve return on investment. Below is where high-speed HDI pricing actually comes from, ordered from most to least impact.
02 / Cost Drivers
Cost Drivers, Ranked
-
Laminate grade
Low-loss and ultra-low-loss materials cost more than FR-4; the right grade is the cheapest that closes the loss budget for your channel length.
-
Layer count & lamination cycles
Each sequential lamination cycle repeats press, drill, plate, and image steps. Reaching the same fan-out in fewer layers via HDI can offset the cycle cost.
-
Impedance tolerance
±10% is standard; ±7% or ±5% adds test, coupon work, and scrap. Specify the tolerance the interface needs, not the tightest available.
-
Added processes
Backdrilling, copper-filled stacked microvias, and smoother copper foil each add steps — applied where the channel needs them.
03 / Buyer Advisory
Buyer Advisory
When you request a quote, send your Gerber or native Altium design files along with the data rate, channel length, impedance target, and layer budget, and we will quote the high-speed PCB manufacturing build your board actually needs.
Ready to scope a high-speed HDI build?
Request a quote with a free DFM & impedance review →01 / Design Tools
High-Speed Design Tools
Customers & PCBark
Our Customers & PCBark Together
01 / FAQ
Frequently Asked Questions
What is the difference between a high-speed PCB and a high-frequency PCB?
High speed describes digital signals with fast edge rates — DDR5, PCIe 5.0, USB4 — where the rise time, not the clock, sets the bandwidth the board has to carry without distortion. High frequency usually means analog RF or microwave energy at a steady carrier, where the dielectric constant stability of the laminate dominates. They overlap in materials and controlled impedance, but a high-speed digital board is engineered around insertion loss, crosstalk, and timing skew across a wide spectrum, while an RF board is tuned to a narrow band. The boards we build are the high-speed digital case.
What impedance tolerance can you hold on controlled-impedance HDI boards?
Our standard controlled impedance is built to 10%, which handles the majority of DDR5 and PCIe routing. If budget is a constraint, we can build to 7% or 5% upon request, verifying the tight impedance with a TDR-tested impedance coupon delivered with the lot. This depends on trace width, dielectric thickness, copper weight, and amount of your stack-up tolerance already allocated to design – why we finalize impedance requirements during DFM, not after fabrication.
How many layers does a DDR5 or PCIe 5.0 PCB need?
There’s not a fixed number — layer count depends on the number of controlled-impedance reference planes needed, and how high-speed pairs fan out from BGAs and connectors. An average DDR5 module typically uses 6-8 layers; dense 5.0 or 100GbE PCIe backplanes will commonly run 12+ layers because any signal layer wants an adjacent solid ground plane to reduce return path inductance. Stack two signal layers between one plane and the crosstalk, and both impedances take a hit. HDI construction helps gain many of the same benefits with fewer layers; microvias replace through-holes and recover routings that a through-hole board consumes with via clearance. This is just one reason that any high-speed design will probably move to HDI even if layer count doesn’t. The layer count is determined during the stack-up review based on your specific impedance requirements.
Which laminate should I use for DDR5 versus PCIe 5.0 versus USB4?
That correlates with data rate and length. DDR5 at moderate lengths can typically be built with a mid-level loss laminate, while high-speed PCIe 5.0 or USB4 will typically need a low-loss laminate like a Megtron-level part to meet the required budget of insertion loss for their specified lengths and speeds; long 100GbE often requires ultra-low-loss types. Really, it’s a loss budget, not a preference in brand – we’ll just match the lowest-cost laminate available that successfully closes the channel and meets all your needs.
What does HDI add over a standard multilayer PCB for high-speed digital?
Use short, copper-filled microvias instead of long through-holes. This nearly eliminates stub effects behind the majority of high-speed reflections, reduces insertion loss, and allows fine-pitch BGAs that a normal board can’t trace.
What are the main cost drivers and lead times for high-speed HDI PCBs?
Cost is driven primarily by laminate grade, layer count, lamination cycles, amount of impedance tolerance specified, and additional processes such as back drilling or including impedance coupons. Ultra-low- and low-loss laminates are obviously more costly than standard FR-4; very precise impedance tolerance will increase test yield and scrap. Build time increases with layer count and lamination cycles – prototypes generally build much quicker than fully qualified impedance-verified lots. Typically, building a stack to fixed loss budget and impedance targets during DFM yields the most cost-efficient result by not over-specifying components for the board layout.
Final Step / Request a Quote
Get Your High-Speed HDI Board Built Right the First Time
Just give us your channel length, data rate, impedance target, and desired layer budget. We’ll review stack-up designs, determine a cost-effective laminate that meets your budget, and quote a controlled-impedance HDI circuit board that includes impedance verification. We draw on more than 16 years of high-speed PCB manufacturing to make sure your channel actually closes.
- Channel length
- Data rate
- Impedance target
- Layer budget
Send the four inputs above — we return a build-ready quote.
Request a High-Speed HDI Quote →DFM & impedance review included with every high-speed HDI quote.
