Designing and Manufacturing 16-24 Layer PCBs: A Complete Engineering Guide

The 16-24 layer pcb resides where the routing density, power-plane count, and signal integrity demands exceed what a 4-12 layer board can deliver – i.e. where most server back planes, telecom switches, and avionics boards actually live. In this paper we discuss stackup architecture, why we should resort to sequential lamination, the approach to blind and buried via implementation, impedance verification, and a scheme for auditing the fabricator prior to releasing a design to manufacturing.

What Actually Counts as a 16-24 Layer PCB

NASA’s board-workmanship standard offers the following definition that’s general enough to apply without strict boundaries: “a composite structure that uses point-to-point interconnections to form an electronic circuit… including constructions that are single-sided, double-sided, multi-layer, rigid, rigid-flex and flex” — a definition broad enough to cover nearly any multilayer board, 16-24 layers included.

The 16-to-24-layer range actually owes more to a structural threshold, however: you require separated ground and power planes instead of just another layer for the actual traces and components, the stackup needs to remain symmetric for laminating without deformation, and when you start adding blind or buried vias, the board won’t just be laid up once anymore.

The Missouri University of Science and Technology 2025 class project study took up a real 24-layer design: 10 signal layers within a 160-mil overall stack up, 1.3 mil stripline dielectric. This is a considerable step up from a 4-6 layer consumer board, and it’s why the design questions raised here, stackup symmetry, lamination ordering, via selection, impedance control, begin to matter at this range in a way they don’t much below it.

Whether the spec sheet calls it a 16 layer PCB, a 20 layer PCB, or simply a high layer count PCB, the dividing line described above stays the same regardless of the exact number in between.

Stackup Design and Layer Arrangement for 16-24 Layers

The ruling principle at this layer count is the same as at 10 layers, just iterated many more times: every signal layer must have an adjacent reference plane, each of the outer layers and inner layers has a dedicated role in the stackup, and the entire stack-up has to be symmetric from top to bottom relative to the center of the board in order to avoid warping during lamination. Rick Hartley, a signal integrity veteran at Applied Innovation, laid out the fundamental physics simply: “since signal layers should always be routed one dielectric layer away from a return plane, having more than six signal layers in a 10-layer stack-up isn’t a good idea.”

“Due to the very thin dielectrics in high-layer-count boards, those of the 10- and 12-layer variety have extremely low plane impedance and excellent signal quality, if properly stacked.”

Rick Hartley, Applied Innovation, EE Times

Scale that rule to 24 layers and the same signal-to-reference-plane discipline holds, which is exactly what the Missouri S&T case study demonstrated in practice: targeting 100 Ω differential impedance on a stripline differential pair signal layer, the design achieved 99.76 Ω (a 0.24 Ω error), -1.19 dB/inch insertion loss against a -1.2 dB/inch target, and -78.29 dB far-end crosstalk against a -60 dB target. That’s what a properly stacked high-layer board looks like when the reference-plane rule is followed consistently, figures from one published academic case study, not a cross-validated industry average, so treat them as a proof point rather than a guaranteed result on every design.

However, this doesn’t happen by itself. One case, for example, with a 24-layer, 3.0mm-thick board had top/bottom layer copper density imbalances serious enough to have failed flatness requirements without correction. Also flagged in that same review was a customer spec for 4mil maximum backdrill stubs that was considered too aggressive given the board’s thickness. It’s risky to maintain such tight stubs on such a thick board while ensuring adequate plating in the vias; 5-6 mil minimum was recommended instead.

Failure to properly balance copper density can result in non-visible failures. One CAM engineer described designing a stackup in which all the power planes were located on one side of the board, with the signal traces all on the opposite side. When finished, the board warped badly after reflow and looked like “a potato chip.” Compounding the problem, the first few units tested fine, and the board’s warpage became apparent in field use only after six months of operation when the warped board had pulled enough BGAs out of contact to cause failures.

Pay close attention to the tier breaks: The 16-24 layer tier is in the “Advanced” to “High-Complexity” tiers, not “Extreme”; it’s when you hit 28 layers or more that the cost curve gets truly steep and each two layers add significantly to the price.

The main point is that it’s all about stackup symmetry and discipline about reference plane that gives the 16-24 layer board the performance, it isn’t the count.

The structural reason a warped stackup tends to fail in the field rather than at the factory is straightforward: a post-lamination flatness check (part of PCBark’s ISO 9001:2015-certified in-house verification) catches copper-density imbalance before assembly, whereas a board that skips that step can pass initial testing and still warp enough, after months inside an aerospace or defense enclosure, to pull BGA balls out of contact.

Why Sequential Lamination Becomes Necessary (and What Materials Survive It)

In the pcb manufacturing process building an otherwise conventional multilayer is done in a single lamination step, all the layers become fused to each other under heat and pressure at once. That breaks down as soon as the design of a 16 to 24 layer build starts to include buried or blind vias, which it usually, though not always does at that layer count.

NASA’s own microvia engineering documentation frames it precisely: “an alternative approach to pin-parallel composite building is a sequential buildup of the layers, which allows buried vias.”

The constraint is on the architecture of the via and the density of the routing, not simply on the layer count – it’s technically possible to construct a 16 to 24 layer design with only through vias in a lower number of cycles.

When this level of signal-layers on high pin-count devices starts happening, you’ll frequently run into vias (that means that the norm is sequential lamination), to one degree or another. A Reddit engineer who does HDI fabrication stated this fairly plainly: “having to use sequential laminations is a big cost adder. Laser drilling from outer to next layer isn’t a big cost adder.

Stacked vias are a big cost adder and greatly limit who can build the board.” Here’s the way that it work out in a 20 layer board: you can make up two sub-laminate’s, and drill through-vias between the sub-laminates and glue the two sub-laminates together. For each new structure with buried vias you’ll add one new lamination step.

Materials must withstand cycles of heat and pressure and not come apart, or “delaminate.” JPL and NASA Glenn Research Center obtained actual process parameters for lamination – a hot-and-pressure oven (an autoclave) operating at 300°C and 100 psi for an hour a cycle – and performed thermal cycles from -125°C to 100°C (no delamination occurred for 21 cycles). Laminate and prepreg materials are qualified to IPC-4101E, which includes specifications for glass transition temperature (Tg), the coefficient of thermal expansion (both X and Z axis) and resistance to CAF (conductive anodic filament) growth, factors that can make or break whether materials make it through more than one pressing cycle.

Bob Willis, a highly-quoted expert in SMT & assembly defects, makes an analogous statement about delamination: Delamination is often erroneously blamed entirely on moisture – in fact the mechanism is generally caused by weak inter-layer bonds and/or contamination introduced during lamination – and the moisture just exploits the weakened adhesion.

“PCB delamination can be subtle or obvious. It is caused by expansion of moisture in the PCB laminate, but that may not be the root cause… poor bonding during manufacturing of the multilayer board or some form of contamination may result in poor adhesion on inner layers, permitting moisture to accumulate.”

Bob Willis, SMT & Assembly Defect Analyst, Printed Circuit Design & Fab

FICT Ltd’s 2026 patent addresses this general class of problem directly: offsetting the conductive-paste via position away from directly above the core through-hole so that resin thermal expansion during lamination bonding doesn’t apply destructive stress to the via, improving long-term reliability for server-motherboard and high-speed interposer applications.

Controlled Impedance and Signal Integrity Across Deep Stackups

Maintaining the same impedance through 16-24 layers is all about the control of dielectric thickness and repetition of reference-plane location through all the lamination steps – it’s the same physics as on a 4-layer board, just with more chances for the deviation to accumulate. Normal fabrication performance holds impedance within 10% and up to 5-7% on an up-charge version with more refined dielectric thickness and tested traces. IPC-6012F’s Amendment 1 (which was rolled into the present version) provides for thinner internal conductor thicknesses than the table previously did.

This offers greater impedance control in the multilayer stacks by reducing variation as copper layer thicknesses decrease.

For controlled-impedance orders, PCBark provide one TDR (time-domain reflectometry) verification report per board, together with 100% flying probe test and AOI for every inner core, before lamination – it isn’t a sampling method. Every core, before final lamination – that’s the verification layer required for any impedance tolerance on a data-sheet. Stub length off a via is one of the bigger uncontrolled variables in a deep stackup’s impedance and insertion-loss budget, which is exactly the problem a recent backdrilling patent addresses directly by re-positioning the via relative to the drill to hold a tighter zero-clearance tolerance.

Blind, Buried, and Stacked Microvia Structures: The Via-Type-to-Lamination-Cycle Cost Map

Each type of via you define on a 16-24 layer board comes with a real cost and a lamination cycle impact – not an abstract “advanced feature” line item. Per IPC-2226A, a microvia is defined as having a diameter less than 0.15mm and aspect ratio up to about 1:1 (though often more like 0.8:1 in practice, like a 4-mil dielectric with a 5-mil drill). Blind and buried via structures generally add 10-30% to fabrication cost depending on the number of HDI layers and the density of microvias – and one real-world Xilinx application note on a 16-layer PCIe stackup illustrated the cost further: each new type of blind or buried via introduced on a given board adds about 30% to the cost of lamination.

The underlying physical constraint for all of this is the aspect ratio that the laser drilling system is capable of drilling with adequate yield. AtlasPCB’s yield impact bands translate this tradeoff clearly: aspect ratios below 6:1 have minimal yield impact; 8:1 to 10:1 require optimization; and above 12:1 you’re into special equipment territory with reduced yields and associated pricing penalties. This happens because the plating ‘throwing power’ – or how much copper actually deposits in the middle of a drilled barrel compared to the surface – goes from 80-90% at 5:1 to 40-55% at 12:1.

Is a High-Layer-Count Board the Same as HDI?

Not automatically. Layer count and HDI (High Density Interconnect) construction are two independent, high-density-routing design axes that may intersect but don’t overlap entirely. Standard, through-via stackup construction typically uses minimum via sizes in the range of 0.2mm for layer counts in the 4-8 range that support around 10Gbps.

HDI constructions employ minimum via sizes of 0.075mm or less on typically 8-32+ layer boards that can support 56-112Gbps and beyond, and the same lamination-reliability discipline covered in a NASA Glenn Research Center flex-circuit lamination study applies just as much to a microvia-heavy HDI build as it does to a conventional through-via stackup. So a 16-24 layer board could be built as a conventional, all-through-via stackup, as a full HDI design, or anywhere in between-layer count alone isn’t definitive. For an in-depth side-by-side comparison, see our HDI vs. multilayer PCB comparison.

A truly counter-intuitive, to state plainly, statement worth mentioning is that more layers isn’t necessarily better. The three separate, independent PCB manufacturers – unrelated in any way to each other – make the exact same point. One expresses it about as starkly as any engineering blog that we could find for this research: “layer count is the symptom you bill for. Stack-up is the disease you actually have.” Another makes it a direct comparison: “a well-designed 4-layer board can outperform a poorly designed 6-layer board. The key is appropriate layer assignment and proper stack-up configuration, not just layer count.” A third simply states it as a common misunderstanding that fabricators are frequently told: “a common misconception is that more layers automatically translate to higher quality… the real determinant of PCB quality lies in rigorous design principles, precise process control, and reliable manufacturing practices.” While we couldn’t find an academic or standards-body source that specifically makes this claim, the fact that independent commercial fabricators say this is certainly a notable point to know even without higher-tier validation.

Where 16-24 Layer Boards Actually Get Used

Servers, HPC, and AI Accelerator Platforms

In the server/high-performance computing (HPC) market for PCBs, which totaled $18 billion in 2023 according to industry market researcher Prismark, more than 60% of these PCBs are 18-24 layer, and the segment is projected to grow at over 20% year-over-year to $25 billion by 2025. On a typical 24-layer server board, a significant allocation of layers is designated to power and ground, usually amounting to around 8 power and 4 ground planes, in order to efficiently manage signal integrity. AI server motherboards, meanwhile, are now trending higher, increasing from 14 layers in 2019 to an average of 18-22 layers by 2024, with products like Dell’s PowerEdge line using 20-layer boards to facilitate AI inference. In related analyses of the AI mainboard market (also referencing the Prismark research but through a different trade publication), a common approach is a hybrid construction that typically uses 20-30 conventional multi-layer core boards, complemented by 2-8 high-density interconnect (HDI) layers for the most signal-intensive regions; this has driven the HDI PCB market category to achieve growth of 17.8% in 2024, outperforming all other PCB types.

Aerospace and Defense

The same factor – high component fan-out – drove avionics and defense electronics towards this range, with an added layer on top of it: IPC-6012FS, a Space and Military Avionics Applications Addendum to IPC-6012F, which serves as the Class 3 quality barrier these boards were built to withstand — a bar comparable in spirit to NASA’s own soldered-connection workmanship standard for flight hardware. A high pin count BGA fanout was one of the primary causes that led many design to be categorized in this range, according to an Electronic Design article by engineer Brendon McHugh: “one of the biggest drivers for large layer stackup is high-pin-count ball grid arrays (BGAs), where special consideration must be given to the ‘breakout’ or ‘fanout’ of the traces.” For more detail about aerospace design criteria, look to our aerospace PCB design guide.

Key takeaway: not every application benefit from maximum layer count. As one practicing fabricator put it in an AMA, high layer count and copper thickness bring “no advantage, really” for applications that don’t need the routing density — “would you rather carry an iPhone or an iHuge.” Match the layer count to the routing and power-domain requirement, not the other way around.

Fabricator Verification: The Fabricator Verification Scorecard

A quote sheet tells you what a fabricator says they can build, it doesn’t tell you whether they can verify it after the fact, and for 16-24 layer boards with blind/buried vias, verification is where reliability risk actually hides — the same class of latent microvia-plating risk documented in NASA’s microvia reliability engineering report. IPC itself has issued a direct industry warning on this point: traditional inspection techniques are no longer an effective quality-assurance tool for detecting microvia-to-target plating failures, meaning a board can pass initial acceptance testing and still fail later during reflow, environmental stress screening, or field service.

This is precisely what PCBark’s own process is built to answer: IPC-6012 Class 2/3 workmanship, TDR-verified impedance reporting on controlled-impedance orders, 100% flying-probe e-test and AOI on every inner core, X-ray on BGA joints, and cross-section/micro-section inspection of inner copper, as part of turnkey EMS service spanning DFM through SMT/THT assembly and functional test, under ISO 9001:2015. Ask any fabricator you’re evaluating the same six questions above; the answers tell you more than a capability chart.

Cost and Lead Time Realities for 16-24 Layer Boards

PCB fabrication costs for this layer range come in different units depending on the source and they don’t quite align to a single figure – which is useful information in itself. One fabricator’s published pricing puts a 24-layer prototype (1-10 pieces) at $800-2,500 per board, with production-volume FR4 builds running $150-400 per board, with premium low-loss materials adding 40-60%. A separately published, independent percentage-based framework indicates that each additional copper layer adds roughly 10-20% to fabrication cost on top of a basic 2-layer board, with a 6-layer board almost doubling the price of a 2-layer of equivalent size – and blind/buried vias or via-in-pad structures add an additional 30-50% on top depending on layer count. Both suggest the same general direction – that cost is growing faster than layers – but neither is a replacement for a project specific quote. Part of that cost curve is the extra press cycle every via-structure change demands, which is exactly the cost driver a 2026 laminated-substrate patent tries to engineer around by reducing the stress a given via places on surrounding material during bonding.

Estimates for global PCB market size are varied enough among market research firms that offering any single figure implies more precision than any single report truly has. A market research report compiled from Korean and Taiwanese trade press and customs data via TrendForce shows a market of roughly $92 billion in 2025 with growth of 28-35% driven by AI; another independent market research firm estimated $74 billion in 2025 growing to $130 billion in 2034; a third estimated the market at $80 billion in 2025 with a 5.2% CAGR through 2032. Treat any specific market size or CAGR figure you see – including these – as directional and not authoritative.

Where the Layer Count Is Heading: AI/ML, 800G Networking, and HPC

AI accelerator and 800G-networking demand is pulling sequential-lamination fabrication capacity tight industry-wide, copper-clad laminate import prices reached $20,728 per ton in March 2026, up 74.5% from a year earlier, per TrendForce’s compilation of Korean and Taiwanese trade press and customs data, the first time import levels have exceeded $20,000/ton since records began in 2000.

For anyone planning a 16-24 layer board on a 2026 timeline, the practical implication is straightforward: lock in fabricator capacity earlier in the design cycle, not after tape-out, the material and process capacity this layer range depends on is under real, dated pressure, not a hypothetical future risk.

It’s not a one-off report. TrendForce’s own research arm states that NVIDIA’s newest generation of Rubin GPUs are “reshape the demand for advanced substrate and PCB material,” carrying substantially more layers than their predecessors. Separate trade reports citing Prismark research corroborate AI mainboards have moved into hybrid 20-30-plus-layer-plus-HDI designs and that the HDI category grew a whopping 17.8% in 2024-the highest of any PCB class. Meanwhile, a networking-focused analyst firm corroborates the 800G/1.6T transition driving the “networking” part of this trend and projects the market for AI scale-out Ethernet to exceed $100B by 2030. Fabricator-side engineering is already responding to that pull: a 2026-filed backdrilling patent aimed at server-motherboard and high-speed interposer applications is one concrete sign of where via-structure engineering is headed as layer counts climb past today’s 16-24 range.

Frequently Asked Questions